CMOS Based SNR Measurement for Wireless Application

Authors

  • Mohd Khuzairi Bin Che Kamarudin Department of Communication Engineering, Universiti Tun Hussein Onn Malaysia, Parit Raja, Johor, Malaysia

DOI:

https://doi.org/10.55447/jaet.02.01.7

Keywords:

Complementary Metal Oxide Semiconductor, Divider Circuit, Multiplier circuit, Signal to Noise Ratio (SNR)

Abstract

This paper presents the design of a CMOS based Signal to Noise Ratio (SNR) detection system. The design system is developed using divider, multiplier and an additional multiplier in a feedback loop. The divider in the designed system produce 1/V of the signal and multiplier produces the average squared SNR signal. The last stage in this design circuit is a low pass filter necessary to implement the desired “average” measure of the signal to noise ratio (SNR). From simulation, the output voltage of SNR is 9.167mVp-p and from practical, the output voltage is 13.2mVp-p.

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Published

2018-06-30

How to Cite

Kamarudin, M. K. B. C. . (2018). CMOS Based SNR Measurement for Wireless Application. Journal of Applied Engineering & Technology (JAET), 2(1), 9–13. https://doi.org/10.55447/jaet.02.01.7

Issue

Vol. 2 No. 1 (2018): Journal of Applied Engineering & Technology (JAET)

Section

Articles

License

Copyright (c) 2018 Journal of Applied Engineering & Technology (JAET)

Creative Commons License

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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